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| LCX027AK 1.4cm (0.55-inch) NTSC/PAL Color LCD Panel For the availability of this product, please contact the sales office. Description The LCX027AK is a 1.4cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel provides full-color representation in NTSC/PAL mode. RGB dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. Features * The number of active dots: 180,000 (0.55-inch; 1.397cm in diagonal) * Horizontal resolution: 400 TV lines * High optical transmittance: 4.2% (typ.) * High contrast ratio with normally white mode: 200 (typ.) * Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible) * High quality picture representation with RGB delta arranged color filters * Full-color representation * NTSC/PAL compatible * Right/left inverse display function * 4:3 and 16:9 aspect switching function Element Structure * Dots Total dots : 827 (H) x 228 (V) = 188,556 Active dots: 800 (H) x 225 (V) = 180,000 * Built-in peripheral driver using polycrystalline silicon super thin film transistors. Applications * Viewfinders * Super compact liquid crystal monitors etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98526-PS LCX027AK Block Diagram HCK2 BLUE GREEN 2 HCK1 (NC) RGT VCK HST VSS 16 15 14 13 EN 12 11 10 9 8 7 6 5 RED 4 3 H Level Conversion Circuit Top/bottom BLK Control Circuit H Shift Register V Level Conversion Circuit V Shift Register CS LC COM Pad -2- COM 1 CLR VST VDD BLK LCX027AK Absolute Maximum Ratings (VSS = 0V) * H and V driver supply voltages VDD * H driver input pin voltage HST, HCK1, HCK2 RGT * V driver input pin voltage VST, VCK CLR, EN, BLK * Video signal input pin voltage GREEN, RED, BLUE * Operating temperature Topr * Storage temperature Tstg -1.0 to +17 -1.0 to +17 -1.0 to +17 -1.0 to +15 -10 to +70 -30 to +85 V V V V C C Operating Conditions (VSS = 0V) Supply voltage VDD 11.4 to 12.6 V Input pulse voltage (Vp-p of all input pins except video signal input pins) Vin 2.6V (more than) Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol COM GREEN RED BLUE BLK HCK1 HCK2 HST Description Common voltage of panel Video signal (G) to panel Video signal (R) to panel Video signal (B) to panel Top/bottom block display pulse Clock pulse for H shift register drive Clock pulse for H shift register drive Start pulse for H shift register drive Pin No. 9 10 11 (12) 13 14 15 16 Symbol RGT CLR EN (NC) VCK VST Vss VDD Description Drive direction pulse for H shift register (H: normal, L: reverse) Improvement pulse for uniformity Enable pulse for gate selection Not connected Clock pulse for V shift register drive Start pulse for V shift register drive GND (H, V drivers) Power supply for H and V drivers -3- LCX027AK Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high resistance of 1M (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) Video signal input VDD From H driver Input 1M Signal line (2) HCK1, HCK2 VDD 250 250 HCK1 250 HCK2 1M 250 1M Level conversion circuit (2-phase input) (3) HST VDD 250 Input 1M 250 Level conversion circuit (singlephase input) (4) RGT, VST, CLR, EN, VCK, BLK VDD 2.5k Input 1M 2.5k Level conversion circuit (singlephase input) (5) COM VDD Input 1M LC -4- LCX027AK Level Conversion Circuit The LCX027AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit voltage is stepped up to VDD inside the panel. This level conversion circuit meets the specifications of a 3.0V power supply of the externally-driven IC. 1. I/O characteristics of level conversion circuit Output voltage (inside panel) (For a single-phase input unit) An example of the I/O voltage characteristics of a level conversion circuit is shown in the figure to the right. The input voltage value that becomes half the output voltage (after voltage conversion) is defined as Vth. The Vth value varies depending on the VDD voltage. The Vth values under standard conditions are indicated in the table below. (HST, VST, EN, CLR, RGT, VCK and BLK in the case of a single-phase input) VDD Example of single-phase I/O characteristics VDD 2 Vth Input voltage [V] VDD = 12.0V Item Vth voltage of circuit Symbol Vth Min. 0.35 Typ. 1.50 Max. 2.60 Unit V Output voltage (inside panel) (For a differential input unit) An example of I/O voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. Although the characteristics, including those of the Vth voltage, are basically the same as those for a single-phased input, the twophased input phase is defined. (Refer to clock timing conditions.) VDD Example of differential I/O characteristics VDD 2 Vth Input voltage [V] 2. Current characteristics at the input pin of level conversion circuit A slight pull-in current is generated at the input pin of the level conversion circuit. (The equivalent circuit is shown to the right.) The current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (Refer to electrical characteristics.) 0 0 Input pin voltage [V] 10 VDD output Input pin current HCK1 input HCK2 input Max. value Level conversion equivalent circuit Pull-in current characteristics at the input pin -5- LCX027AK Input Signals 1. Input signal voltage conditions (VSS = 0V, VDD = 11.4 to 12.6V) Item H driver input voltage (HST, HCK1, HCK2, RGT) V driver input voltage (VST, VCK1, VCK2, CLR, EN) Video signal center voltage Common voltage of panel (Low) (High) (Low) (High) Symbol VHIL VHIH VVIL VVIH VVC VCOM Min. -0.35 2.6 -0.35 2.6 5.8 Typ. 0.0 3.0 0.0 3.0 6.0 Max. 0.35 3.5 0.35 3.5 6.2 VVC Unit V V V V V V VVC - 0.3 VVC - 0.15 Item Video signal input range Video signal input white level Symbol Vsig VsigL Min. VSS + 1.3 0.5 Typ. Max. VDD - 1.8 Unit V V Note) Video signal shall be symmetrical to VVC. Supplement) Video signal input range is set within the range shown below for VDD and VSS. Also, video signal white level is defined for VVC as shown below. VDD VDD - 1.8 VsigL VVC White level VsigL Video signal input range Max. VDD - 1.8 [V] Min. VSS + 1.3 [V] VSS + 1.3 VSS -6- LCX027AK 2. Clock timing conditions (Ta = 25C, Input voltage = 3.0V, VDD = 12.0V) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn2 rise time HCK Hckn2 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time Clr fall time CLR Clr pulse width Clr fall to Hst rise time Vck rise/fall to Clr fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time En rise time EN En fall time Vck rise/fall to En fall time BLK rise time BLK3 BLK fall time BLK pulse width BLK fall to Clr fall time Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr twClr toHst thVck trVst tfVst tdVst thVst trVck tfVck trEn tfEn tdVck trBlk tfBlk twBlk toClr 600 1.0 700 800 -100 0 -50 -50 32 -32 3400 1850 400 3500 1950 500 -15 -15 0 0 -100 -200 60 -120 Min. Typ. Max. 30 30 100 -50 30 30 15 15 100 100 3600 2050 600 100 100 50 -20 100 100 100 100 100 100 100 ms ns ns s ns Unit 2 Hckn means Hck1, Hck2. (fHckn = 2.75MHz, fVckn = 7.865kHz) 3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS. -7- LCX027AK HST 10% trHst 4 Waveform 90% 90% 10% tfHst Conditions HCKn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst Hst data set-up time tdHst 50% HST HCK1 50% 50% 50% Hst data hold time thHst tdHst thHst 90% 10% HCKn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn2 rise time Hckn2 fall time HCK trHckn 90% 2 HCKn 10% tfHckn 4 trHckn tfHckn HCKn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 135ns thHst = -135ns Hck1 fall to Hck2 rise time 50% 50% to1Hck HCK1 50% 50% tdHst = 135ns thHst = -135ns Hck1 rise to Hck2 fall time to2Hck HCK2 to2Hck to1Hck Clr rise time trClr 90% CLR 10% 90% 10% Clr fall time tfClr trClr tfClr HCKn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Clr pulse width CLR Clr fall to Hst rise time twClr HST 50% toHst CLR 50% twClr 50% toHst HCKn2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns VCK 50% Vck rise/fall to Clr fall time thVck CLR 50% thVck -8- LCX027AK VST 10% trVst 4 Waveform 90% 90% 10% tfVst Conditions VCK duty cycle 50% tfVst Vst data set-up time tdVst 50% VST 50% 50% 50% VCK duty cycle 50% Vst data hold time thVst VCK tdVst 90% VCK 10% thVst 90% 10% Vck rise time VCK Vck fall time trVck tfVck VCK duty cycle 50% tdVst = 32s thVst = -32s trVck tfVck En rise time trEn EN 90% 10% 10% 90% En fall time EN Vck rise to En rise time tfEn 4 tfEn trEn VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVck VCK 50% 50% 50% 50% Vck rise to En fall time tdVck EN tdVck 90% 10% tdVck 90% 10% tfBlk VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns BLK rise time trBlk BLK fall time BLK BLK pulse width tfBlk 4 BLK trBlk twBlk 50% twBlk 50% BLK fall to Clr fall time 4 Definitions: toClr CLR 50% The right-pointing arrow ( The left-pointing arrow ( The black dot at an arrow ( ) means +. ) means -. ) indicates the start of measurement. -9- LCX027AK Electrical Characteristics 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Symbol CHckn CHst IHck1 IHck2 IHst IRgt Csig -500 -500 -300 -100 Min. (Ta = 25C, VDD = 12.0V, Input voltage = 3.0V) Typ. 5 5 -130 -150 -20 -15 135 145 Max. 10 10 Unit pF pF A A A A pF HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VST EN CLR VCK BLK Symbol CVck CVst IVst IEn IClr IVck IBlk Min. Typ. 5 5 Max. 10 10 Unit pF pF Condition -100 -15 A VST, EN, CLR, VCK, BLK = GND 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) Symbol PWR Min. Typ. 30 Max. 50 Unit mW 4. VCOM input resistance Item VCOM - Vss input resistance Symbol Rcom Min. 0.5 Typ. 1 Max. Unit M - 10 - LCX027AK Electro-optical Characteristics Item Contrast ratio VDD = 12.0V Vsig = 6.0 4.0V 60C 25C 60C R X Y X Y X Y 25C 60C 25C 60C 25C 60C Symbol CR4.060 CR4.025 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 5 4 3 Measurement method 1 2 Min 70 70 3.8 0.580 0.300 0.250 0.550 0.105 0.070 1.1 1.0 1.5 1.4 2.2 2.1 -- -- -- -- 6 -- -- 7 8 9 -- -- 5.75 (Ta = 25C, NTSC mode) Typ. 200 200 4.2 0.620 0.340 0.290 0.590 0.140 0.110 1.7 1.6 2.1 2.0 2.6 2.5 -0.10 0.07 32 16 55 25 -- -- 5.85 Max. -- -- -- 0.660 0.380 0.330 0.630 0.175 0.150 2.2 2.1 2.5 2.4 3.2 3.1 -0.25 0.45 100 40 150 60 -40 20 5.95 dB s V ms V V CIE standards % Unit -- Optical transmittance Chromaticity G B V90 V-T characteristics V50 V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time Optimum Vcom voltage R vs. G V50RG B vs. G V50BG 0C 25C 0C 25C 60C ton0 ton25 toff0 toff25 F 60 min. YT60 VCOMopt - 11 - LCX027AK 3.5mm Back Light Luminance Meter Measurement Equipment LCD panel Back light: color temperature 8500K, +0.004uV (25C) Back light spectrum (reference) is listed on another page. Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR4.0) is given by the following formula (1). CR4.0 = L4.0 (White) ...(1) L4.0 (Black) L4.0 (White): Surface luminance of the TFT-LCD panel at VDD = 12.0V, VVC = 6.0V, VCOM = 5.85V and the RGB signal amplitude VAC = 0.5V. L4.0 (Black): Surface luminance of the panel at VAC = 4.0V. - 12 - LCX027AK 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) x 100 [%] ...(2) Luminance of Back Light L (White) is the same expression as defined in the "Contrast Ratio" section. 3. Chromaticity Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses Chromaticity of x and y on the CIE standards here. Signal amplitudes (VAC) supplied to each input R input R Raster G B 0.5 4.0 4.0 G input 4.0 0.5 4.0 B input 4.0 4.0 0.5 (Unit : V) 4. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (Transmittance at VAC = 0.5V is 100%.) Transmittance [%] 90 50 10 V90 V50 V10 5. Half Tone Color Reproduction Range Half tone color reproduction range of the LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G, B raster modes which correspond to 50% of transmittance, V50R, V50G and V50B respectively. V50RG and V50BG, the voltage differences between V50R and V50G, V50B and V50G, are simply given by the following formulas (3) and (4) respectively. V50RG = V50R - V50G ...(3) V50BG = V50B - V50G ...(4) - 13 - VAC - Signal amplitude [V] 100 V50RG V50BG Transmittance [%] 50 R raster G raster B raster 0 V50R V50B V50G VAC - Signal amplitude [V] LCX027AK 6. Response Time Response time ton and toff are defined by the formulas (5) and (6) respectively. 4.0V Input signal voltage (waveform applied to the measured pixels) ton = t1 - tON ...(5) toff = t2 - tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 0.5V 6.0V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20log AC { DC component }...(7) component R, G, B input signal condition for gray raster mode is given by Vsig = 6.0 V50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 8. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 6.0 VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct. Monoscope signal conditions: Vsig = 6.0 4.0 or 6.0 2.0 (V) (shown in the right figure) VCOM = 5.85V Black level 4.0V 2.0V 6.0V 2.0V 4.0V White level 0V Vsig waveform - 14 - LCX027AK 9. Method of Measuring the Optimum Vcom There are two methods of measuring the optimum Vcom using the photoelectric element. 9-1. Method of Measuring Flicker In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. 9-2. Method of Measuring Contrast In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom. Example of Back Light Spectrum (Reference) 0.6 0.4 0.2 0 380 480 580 Wave length 380 - 780 [nm] 680 780 - 15 - LCX027AK Description of Operation 1. Color Coding Color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display. Gate SW dummy1 to 4 Gate SW Gate SW Gate SW Gate SW Gate SW dummy5 to 8 B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G Photo-shielding B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G 827 14 800 13 - 16 - 1 225 228 Active area 2 LCX027AK 2. LCD Panel Operations * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 225 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the gate lines from the top to bottom of the panel. * The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by controlling the enable and VCK pin. The enable pin should be High when not in use. * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period. * Scanning direction of horizontal shift register can be switched with RGT pin. Scanning direction is left to right for RGT pin at High level; and right to left for RGT pin at Low level. (These scanning directions are from a front view.) Normally, set to High level. * Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 225 x 800 dots to display a picture in a single vertical scanning period. * Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is required to apply video signal to the panel. * The video signal shall be input with polarity-inverted system in every horizontal cycle. * Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle are shown below. HCK1 and HCK2 should be inverted to display the left-direction horizontal scanning (RGT = Low level). This inversion enables the center of the image to be fixed by eliminating offsets. (When an example of system mentioned on this data sheet is used, TG performs this operation automatically.) (1) Vertical display cycle VD VST VCK 1 2 224 225 Vertical display cycle 225H (14.3ms) (2) Horizontal display cycle (right scan) BLK HST 270 HCK1 1 2 3 4 5 6 271 HCK2 Horizontal display cycle (48.4s) The horizontal display cycle consists of 800/3 = 267 clock pulses because of RGB simultaneous sampling. Refer to Description of Operation "3. RGB Simultaneous Sampling." - 17 - LCX027AK 3. RGB Simultaneous Sampling Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R, G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block diagrams are as follows. The LCX027AK has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between B and G signals. (1) Sample and hold (right scan) B S/H CKB S/H CKG S/H CKR S/H CKG S/H CKG AC Amp 4 BLUE R AC Amp 3 RED G AC Amp 2 GREEN HCKn CKB CKR CKG (2) Delay circuit (right scan) B Delay Delay AC Amp 4 BLUE R Delay AC Amp 3 RED G AC Amp 2 GREEN - 18 - LCX027AK LCX027AK LCX027AK Example of Color Filter Spectrum (Reference) 100 Color Filter Spectrum R 80 G B 60 Transmittance [%] 40 20 0 400 500 Wavelength [nm] 600 700 - 19 - LCX027AK Color Display System Block Diagram (1) An example of dual-chip display system is shown below. +12V +5V +12.0V RED Composite video Decoder/Driver CXA1785AR GREEN Y/C BLUE Y/color difference SYNC FRP +3V VCOM LCD panel NTSC/PAL LCX027AK HST HCK1 HCK2 VST TG CXD2458AR BLK VCK EN CLR (Refer to CXD2458AR data sheet.) RGT - 20 - LCX027AK Color Display System Block Diagram (2) An example of single-chip display system is shown below. +12V +4.5V +3V +12.0V RED Composite video GREEN Y/C BLUE Y/color difference VCOM LCD panel NTSC/PAL LCX027AK HST HCK1 HCK2 VST VCK EN CLR CXA2503AR (Refer to CXA2503AR data sheet.) RGT When the CXA2503AR is used, BLK (Pin 5) of the LCD panel should be grounded to VSS. - 21 - LCX027AK Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. - 22 - LCX027AK Package Outline 14.0 0.3 8.5 0.05 Unit: mm Thickness of the connector 0.3 0.05 4 1.2 0.3 1 S-C K1 5 4-R 1.0 3 25.5 0.8 34.8 0.8 6 17.8 0.15 Active Area Incident light Active Area 6 7.7 0.25 2 (11.2) 9.0 0.25 18.0 0.15 (8.3) 2.7 0.15 No x 15 = 7.5 0.03 Description FPC Molding material Outside frame Reinforcing board P 0.5 0.02 1 0.5 0.15 3.0 0.3 4.0 0.5 + 0.04 0.35 - 0.03 0.5 0.1 2 3 4 PIN 1 PIN 16 5 Reinforcing material 6 Polarizing film weight 1.3g electrode (enlarged) - 23 - |
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